1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit whereby a high degree of integration can be achieved, and, in particular, to a method for manufacturing a semiconductor integrated circuit whereby the area of the surface occupied by an isolating region can be limited and self-alignment of the isolating region and the integrated circuit element regions is assured.
2. Description of the Background Art
At the present time, a method considered to be one of the most effective isolation methods among the methods of electrically isolating the various integrated circuit elements formed on a semiconductor integrated circuit substrate is the vertical isolation method disclosed in Japanese Patent Laid-Open No. 136250/1985.
In this vertical isolation method, first, as shown in FIG. 1, an N.sup.+ -type buried region 81 is formed by selectively depositing antimony (Sb) on a semiconductor substrate 80 for which a P-type silicon substrate is used. Next, a lower isolating region 83 is formed by selectively depositing boron (B) on the surface of the substrate 80, enclosing the N.sup.+ -type buried region 81.
Following this, as shown in FIG. 2, an N.sup.- -type epitaxial layer 85 is formed to a specified thickness over the entire surface of the semiconductor substrate 80 by the commonly known vapor growth method. At this time, the buried region 81 and the lower isolating region 83 are slightly diffused to a vertical direction.
Then, as shown in FIG. 3, by means of a diffusion method, an upper isolating region 84 is formed by selective diffusion from the surface of the epitaxial layer 85, and simultaneously a lower isolating region 83 is diffused upward from the surface of the semiconductor substrate 80, linking to the isolating region 84 to form an isolating region 82.
This diffusion method is carried out at about 1,200.degree. C. over three to four hours. When the thickness of the epitaxial layer 85 is 13 .mu.m, the upper isolating region 84 is diffused to a depth of about 10 .mu.m, and the lower isolating region 83 is diffused upward to a depth of about 5 .mu.m. Because the diffused region 82 is also diffused from the diffusing window surface in the lateral direction in proportion to the diffusion depth, the width of the isolating region 82 eventually reaches about 24 .mu.m at the surface of the epitaxial layer 85 and about 14 .mu.m at the surface of the semiconductor substrate. At this time the buried region 81 also is diffused to a depth of about 4 .mu.m.
Then, as shown in FIG. 4, a P-type base region 87 is produced by selective diffusion in an island 86 formed by the epitaxial layer 85 which is enclosed by the isolating region 82, followed by forming an N.sup.+ -type emitter region 88 and a collector contact region 89 by selective diffusion to provide an NPN-type transistor.
Because the lateral diffusion at the surface of the epitaxial layer is suppressed, the above-mentioned vertical isolation method has the feature of being able to form extremely fine semiconductor integrated circuits in comparison with the method of forming an isolating region by diffusion from an epitaxial layer surface only. However, because the upper and lower isolating regions 84, 83 of the isolating region 82 are simultaneously formed by diffusion, it is necessary to diffuse the upper isolating region 84 to a moderately greater depth than the lower isolating region 83 in consideration of, such as, impurity concentration or the like. For this reason, the time for diffusion is lengthened by three to four hours and the lateral diffusion of the upper isolating region 84 increases, so that the surface area of the epitaxial layer 85 is largely occupied by the upper isolating region 84. This method has thus a drawback of insufficient improvement in a degree of integration.
Furthermore, in a method of forming the upper isolating region 84 shown in FIG. 3 and the base region 87 shown in FIG. 4 by diffusion, first a doping window (a window for the introduction of dopant) is formed, and the dopant is diffused from this doping window. For this reason, the position of this doping window is deviated from the right position in the alignment of a photo mask and in the etching. This is a second drawback of this method.
The configuration of and a manufacturing method for a bipolar transistor were also discussed in detail in the Latest LSI Process TechnologyApr. 25, 1984 published by Industrial Board of Inquiry.
FIG. 5 shows the configuration of the bipolar transistor disclosed in the above literature. This bipolar transistor comprises a collector region 94 which is an island itself formed from a lower isolating region 92 and an upper isolating region 93 in an N-type epitaxial layer 91, a P-type base region 95 formed within this island, and an N.sup.+ -type emitter region 96 formed within the base region 95.
This type of bipolar transistor is manufactured by a method comprising:
a first step, wherein an SiO.sub.2 film is formed on a P-type semiconductor substrate 90, a doping window for the buried layer 92 is formed in the SiO.sub.2 film, and antimony is selectively doped in the P-type semiconductor substrate 90 through the doping window;
a second step, wherein an SiO.sub.2 film is again formed on the P-type semiconductor substrate 90, a doping window for the lower isolating region 92 is formed in this SiO.sub.2 film, and the semiconductor substrate 90 is selectively doped with boron through the doping window;
a third step, wherein, after the epitaxial layer 91 is grown on the surface of the semiconductor substrate 90, a SiO.sub.2 film is formed on the surface of the epitaxial layer 91;
a fourth step, wherein a doping window for the upper isolating region 93 is formed in the SiO.sub.2 film on the surface of the epitaxial layer 91, and the epitaxial layer 91 is selectively doped with boron through the doping window;
a fifth step, wherein the semiconductor substrate 90 is heat-treated, the various regions which were doped in the foregoing steps are diffused, and the lower isolating region 92 and the upper isolating region 93 are linked;
a sixth step, wherein a doping window for the base region 95 is formed in the SiO.sub.2 film on the surface of the epitaxial layer 91, the epitaxial layer 91 is selectively doped with boron through the doping window to form a base region 95; and
a seventh step, wherein doping windows for the emitter region 96 and for a collector contact region 97 are formed in the SiO.sub.2 film on the surface of the epitaxial layer 91, and the epitaxial layer 91 is doped with phosphorous (P) through the doping window to form the emitter region 96 and the collector contact region 97.
However, because the upper isolating region 93, the base region 95, and the collector contact region 97 formed in the fourth, sixth, and seventh steps are selectively doped through different SiO.sub.2 films, there is concern that the positions which these regions occupy will deviate from the design values, as shown by the dotted lines in FIG. 5, because of the mask alignment required to form the doping windows in each SiO.sub.2 film or because of the subsequent etching. For this reason, the spacing of these regions must be designed to provide a preset allowance so that contact between these regions from the diffusion treatment is avoided. This is an obstacle to high integration.
In addition, when the depth of diffusion of the upper isolating region 93 reaches 10 .mu.m, the upper isolating region 93 also extends to the same extent in the lateral direction. Because of this, the each length of the spacings of the upper isolating region 93 and the other regions must exceed the length of the diffusion depth of the upper isolating region 93 by about 2 .mu.m of a margin. This interferes with the degree of integration of the semiconductor integrated circuit.